1. Field of the Invention
The present invention relates to a test circuit and, more specifically, it relates to a test circuit incorporated in a substrate for testing each of the circuit portions constituting a circuit such as LSI.
2. Description of the Prior Art
Conventionally, in a device in which a plurality of circuits are fabricated on a substrate, such as LSI or VLSI, the test of each of the circuits has been carried out by incorporating a shift register on the same substrate. One example of such test circuit is disclosed in "LSI/VLSI Testability Design" by Frank F. Tsui, 1987, pp. 102-113.
FIG. 1 is a schematic block diagram showing one example of a conventional test circuit employing such a shift register as described in the foregoing. Referring to the figure, the test circuit is constituted by a plurality of shift registers 4a to 4h connected in series between an input terminal 1 and an output terminal 2, and the circuit tests each of the circuit portions 3a to 3f. Each of the circuit portions 3a to 3f is formed on the same semiconductor substrate, constituting a prescribed device as a whole. The shift registers 4a to 4h are formed on the same semiconductor substrate as the circuit portions 3a to 3f.
The operation of the conventional circuit shown in FIG. 1 will be hereinafter described. A test pattern signal is externally inputted to the input terminal 1 successively for carrying out test for each of the circuit portions 3a to 3f. On this occasion, each of the shift registers 4a to 4f is shifted for the necessary times, whereby the test pattern signal which is to be inputted to the circuit portion 3a is stored in the shift register 4a; the test pattern signal which is to be inputted to the circuit portion 3b is stored in the shift register 4b; the test pattern which is to be inputted to the circuit portion 3c is stored in the shift register 4c; the test pattern signal which is to be inputted to the circuit portion 3d is stored in the shift register 4d; the test pattern signal which is to be inputted to the circuit portion 3e is stored in the shift register 4e; and the test pattern signal which is to be inputted to the circuit portion 3f is stored in the shift register 4f, respectively. Thereafter, the test pattern signal stored in each of the shift registers 4a to 4f is inputted to each of the circuit portions 3a to 3f in parallel. Consequently, each of the circuit portions 3a to 3f carries out certain operation based on the inputted test pattern signal. The result of the operation of each of the circuit portions 3a to 3f is applied to one of the shift registers. More specifically, the result of operation of the circuit portion 3a is applied to the shift register 4d, the result of operation of the circuit portion 3b is applied to the shift register 4c, the result of operation of the circuit portion 3c is applied to the shift register 4f, the result of operation of the circuit portion 3d is applied to the shift register 4e, the result of operation of the circuit portion 3e is applied to the shift register 4h and the result of operation of the circuit portion 3f is applied to the shift register 4g, respectively, and these results are stored therein. By shifting each of the shift registers 4c to 4h for the necessary times, the result of operation of each of the circuit portions 3a to 3f is outputted from the output terminal 2. Whether each of the circuit portions 3a to 3f is properly operating or not can be tested by checking the result of operation of each of the circuit portions 3a to 3f obtained from the series of operation.
As described above, in a conventional test circuit, the shift registers are connected in series, so that even if the circuit portion which is distant from the input terminal 1 only is to be tested, the test pattern signal must be successively shifted through the shift registers on the way. For example, if the circuit portion 3e is to be tested, the test pattern signal is inputted to the shift register 4e after it passes through the shift registers 4a to 4d. Therefore, the number of shifting operation becomes large, and it takes much time for testing.